The MC14518B dual BCD counter and MC14520B dual binary counter are constructed using MOS P-channel and N-channel enhancement mode devices in a monolithic structure. Each consists of two identical, independent, internally synchronous 4-stage counters. These counter stages are D-type flip-flops with interchangeable clock and enable lines for incrementing on positive or negative transitions as required when cascading multiple stages. Each counter is cleared by applying a high level on the reset line. Also, the MC14518B will calculate all undefined states within two clock segments. These complementary MOS up-count counters are primarily intended for multi-level synchronous or ripple counting applications requiring low power consumption and/or high noise immunity.
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