逻辑器件/收发器/编码器

Direction: Upper Number of elements: 1 Unit number of bits: 10 Reset method: Asynchronous Timing method: Synchronous Count rate: 5.5MHz Trigger type: positive edge Power supply voltage: 3V~15V Quiescent current (maximum value): 20uA Different V, maximum Maximum Propagation Delay at CL: 170ns@15V,50pF Low Level Output Current (IOL): 3.4mA High Level Output Current (IOH): 3.4mA Logic Level-High: 3.5V~11V Logic Level-Low: 1.5V~4V Operating temperature: -40℃~+85℃

SN74CBT3125C Quad FET Bus Switch with -2V Undershoot Protection

6-Channel, 2V to 5.5V Inverter 14-PDIP -40 to 125

The NLSV2T244 is a 2-bit configurable dual supply voltage level translator. The input An and output Bn ports are designed to track two different supply rails, VCCA and VCCB, respectively. Both supply rails are configurable from 0.9 V to 4.5 V, allowing universal low-voltage conversion from the input An to output Bn ports.

LVPECL to LVTTL

Enhanced Product Single 2-Input, 1.65V to 5.5V NOR Gate 5-SC70 -55 to 125

4-Channel, 2-Input, 2V to 5.5V AND Gate 14-SOIC -40 to 125

SN74LVC125A-Q1 Automotive Quad Bus Buffer Gate with 3-State Outputs

Six inverting Schmitt triggers

CD74HC573 High-Speed ​​CMOS Logic Octal Transparent Latches with 3-State Outputs

The LVX74 is a dual D-type flip-flop with asynchronous Clear and Set inputs, and complementary (Q, Q#) outputs. The information on the input is transferred to the output on the rising edge of the clock pulse. After the "Clock" input threshold voltage is exceeded, the "Data" input is latched and no existing information can be passed to the output until the next rising edge of the "Clock" input. Asynchronous input: Low input of S#D (set) will set Q high, low input of C#D (clear) will set Q low Clear and set are independent of clock, C Simultaneous low on #D and S#D causes both Q and Q# to be high

CD4013B CMOS Dual D-Type Flip-Flop