逻辑器件/收发器/编码器

16-Channel, 2.7V to 3.6V Buffer with 3-State Outputs 48-TVSOP -40 to 85

The MC14018B contains five Johnson counter stages that can be preset and reset asynchronously. These counters are synchronous and increment on the rising edge of the clock. Presetting is accomplished with a logic 1 on the Preset Enable input. Data on the Jam inputs will then be transferred to their respective Qbar outputs (inverted). A logic 1 on the reset input will put all Qbar outputs into a logic 1 state. A divide by 2 to 10 can be accomplished by connecting the appropriate Qbar output to the data input as shown in the function selection table. The MC14018B includes an anti-lock gate to ensure correct counting sequence.

8-input general-purpose shift/storage register with common parallel I/O pins and asynchronous reset 20-SOIC -55 to 125