逻辑器件/收发器/编码器

16-Channel, 2V to 5.5V Buffer with 3-State Outputs 48-TVSOP -40 to 85

The MC14518B dual BCD counter and MC14520B dual binary counter are constructed using MOS P-channel and N-channel enhancement mode devices in a monolithic structure. Each consists of two identical, independent, internally synchronous 4-stage counters. These counter stages are D-type flip-flops with interchangeable clock and enable lines for incrementing on positive or negative transitions as required when cascading multiple stages. Each counter is cleared by applying a high level on the reset line. Also, the MC14518B will calculate all undefined states within two clock segments. These complementary MOS up-count counters are primarily intended for multi-level synchronous or ripple counting applications requiring low power consumption and/or high noise immunity.

8-Bit Parallel Load Shift Register 16-SO -40 to 85

High Speed ​​CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register 14-SOIC -55 to 125