逻辑器件/收发器/编码器

16-Channel, 1.65-V to 3.6-V Buffer with Bus Hold and 3-State Outputs 48-TVSOP -40 to 85

The MC74AC4040 consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next flip-flop, with half the frequency at each output of the previous one. The state of the counter advances once on the negative going edge of the clock input. Reset is asynchronous and active high. Due to internal ripple delays, the state changes of the Q outputs do not occur simultaneously. Therefore, the decoded output signal is prone to decode spikes and may have to be gated with the MC74AC4040's clock for some designs.